The present disclosure relates to a semiconductor integrated circuit device including standard cells (hereinafter, simply referred to as “cells” as appropriate) including fin structure transistors or nanowire field effect transistors (FETs).
A standard cell system is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. The standard cell system refers to a system in which an LSI chip is designed by preparing a basic unit having a specific logical function (an inverter, a latch, a flip-flop, a full adder, or any other component, for example) as a standard cell in advance, arranging a plurality of standard cells on a semiconductor substrate, and connecting the standard cells together through an interconnect.
In recent years, in the field of semiconductor devices, use of fin structure transistors (hereinafter, referred to as fin transistors) has been developed. FIG. 9 is a schematic diagram of an outline of a fin transistor. Unlike two-dimensional structure metal oxide semiconductor (MOS) transistors, a source and a drain of a fin transistor have a bulging three-dimensional structure called a fin. A gate is placed to surround this fin. This fin structure causes a channel region to be formed by three faces of the fin and thus allows channel controllability to be much higher than ever before. Consequently, effects such as a reduction in leakage power, improvement in on-state current, and a reduction in operating voltage are obtained, and the performance of the semiconductor integrated circuit improves. Attention is also being given to nanowire FETs as one of the three-dimensional structure transistors.
United States Patent Publication No. 2014/0167815 (FIG. 4) discloses a configuration of a filler cell used for filling the gap between each adjacent pair of cells. This filler cell has a fin structure having two ends that each terminate between an associated pair of gates.